TSMC is pushing its 3D chip-stacking roadmap towards finer interconnect pitches and tighter integration as advanced packaging becomes a larger part of performance scaling for AI and high-performance ...

Apple is expected to use TSMC's new 2nm process and SoIC-X (System on Integrated Chip) advanced packaging technology in the second half of 2025, according to new reports. AMD was the first to adopt ...

TL;DR: Apple is collaborating with TSMC to adopt advanced WMCM and SoIC packaging technologies for its next-generation A20 and server chips in 2026. These innovations enable ultra-dense chip stacking, ...

The problem is well-known: programming and debug headers consume valuable board space and the connectors cost money. Especially troublesome are the ubiquitous 100-mil pin headers, not because they’re ...

NVIDIA’s GTC has revealed plans to launch an enhanced Rubin Ultra in 2027, while its next-generation architecture, Feynman, is also coming into view for 2028. According to Commercial Times, SoIC ...

TSMC's 3D Fabric advanced packaging and testing plant, AP6, has officially started operation. Advanced packaging and testing providers have indicated that the 3D Chiplet and System-on-Integrated-Chip ...

Nvidia is expected to use TSMC's 3D SoIC (system on integrated chips) stacking and chiplet packaging technology in its high-end processors set to debut between 2024 and 2025, according to sources in ...

TSMC has reportedly secured four major clients for its latest SoIC packaging – AMD, Nvidia, Broadcom, and Apple. The chip manufacturer is actively working on increasing its next-generation chip ...

[Pyra] was looking for a way to reprogram some ATtiny13 microcontrollers in a SOIC package. He’s re-engineering some consumer electronics so adding an ISP header to the design isn’t an option. He had ...

Allegro MicroSystems had introduced 1MHz bandwidth current sensors that can measure hundreds of amps – the first fruit of its acquisition of Crocus Technologies. The technology is tunneling ...

IXYS Corporation announced its new 60 V, dual and normally open solid-state relay with the highest current rating in a SOIC package. It provides 400 V of input-to-output isolation; and comprises two ...